<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
  <head>
    <title>GICM_SETSPI_SR</title>
    <link href="insn.css" rel="stylesheet" type="text/css"/>
  </head>
  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICM_SETSPI_SR, Set Secure SPI Pending Register</h1><p>The GICM_SETSPI_SR characteristics are:</p><h2>Purpose</h2>
        <p>Adds the pending state to a valid SPI.</p>

      
        <p>A write to this register changes the state of an inactive SPI to pending, and the state of an active SPI to active and pending.</p>
      <h2>Configuration</h2><p>This register is present only when GICM_TYPER.SR == 1. Otherwise, direct accesses to GICM_SETSPI_SR are <span class="arm-defined-word">RES0</span>.</p>
        <p>When <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.DS==1, this register is WI.</p>
      <h2>Attributes</h2>
        <p>GICM_SETSPI_SR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="19"><a href="#fieldset_0-31_13">RES0</a></td><td class="lr" colspan="13"><a href="#fieldset_0-12_0">INTID</a></td></tr></tbody></table><h4 id="fieldset_0-31_13">Bits [31:13]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-12_0">INTID, bits [12:0]</h4><div class="field">
      <p>This field is an alias of <a href="ext-gicd_setspi_sr.html">GICD_SETSPI_SR</a>.</p>
    </div><h2>Accessing GICM_SETSPI_SR</h2>
        <p>Writes to this register have no effect if:</p>

      
        <ul>
<li>The value is written by a Non-secure access.
</li><li>The value written specifies an invalid SPI.
</li><li>The SPI is already pending.
</li></ul>

      
        <p>16-bit accesses to bits [15:0] of this register must be supported.</p>
      <h4>GICM_SETSPI_SR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Distributor</td><td>MSI_base</td><td><span class="hexnumber">0x0050</span></td><td>GICM_SETSPI_SR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When GICD_CTLR.DS == 1, accesses to this register are <span class="access_level">WI</span>.
          </li><li>When GICD_CTLR.DS == 0 and an access is Secure, accesses to this register are <span class="access_level">WO</span>.
          </li><li>When GICD_CTLR.DS == 0 and an access is Non-secure, accesses to this register are <span class="access_level">WI</span>.
          </li><li>When GICD_CTLR.DS == 0, FEAT_RME is implemented and an access is Root, accesses to this register are <span class="access_level">WO</span>.
          </li><li>When GICD_CTLR.DS == 0, FEAT_RME is implemented and an access is Realm, accesses to this register are <span class="access_level">WI</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
</html>
